- PD_ISOVCC domain is the area where the power can be turned off. - PD_VBATT domain is the area where the RTC/backup register is located, works on battery power when the power of . The power to these domains are controlled with the help of firmware. Linux cannot do control itself as the CPU is in the PD_ISOVCC. If you look at picture 41.3 Power mode transition [1] it is mentioned the relation b/w these power domains (controlled by PMIC though firmware) and the supported power saving modes: ALL_ON, AWO, VBATT. Thank you, Claudiu Beznea [1] https://pasteboard.co/4ureEUnyCfV8.png > > Cheers, > Biju > >> + >> + resets: >> + items: >> + - description: VBATTB module reset >> + >> + renesas,vbattb-load-nanofarads: >> + description: load capacitance of the on board crystal oscillator >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 4000, 7000, 9000, 12500 ] >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - power-domains >> + - resets >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/r9a08g045-cpg.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/interrupt-controller/irq.h> >> + >> + vbattb@1005c000 { >> + compatible = "renesas,r9a08g045-vbattb"; >> + reg = <0x1005c000 0x1000>; >> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; >> + clock-names = "bclk", "rtx"; >> + #clock-cells = <1>; >> + power-domains = <&cpg>; >> + resets = <&cpg R9A08G045_VBAT_BRESETN>; >> + renesas,vbattb-load-nanofarads = <12500>; >> + }; >> -- >> 2.39.2 >> >
