On 02/09/2024 03:05, Shawn Guo wrote:
> On Sat, Aug 31, 2024 at 12:28:21PM +0200, Krzysztof Kozlowski wrote:
>> Bindings for other NXP pin controllers expect pin configuration nodes in
>> pinctrl to match certain naming, so adjust these as well, even though
>> their bindings are not yet in dtschema format.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>> ---
>>
>> - pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
>> fsl,pins = <
>> MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9
>> MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9
>> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi
>> index a1ea33c4eeb7..79d80632ee45 100644
>> --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi
>> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi
>> @@ -436,7 +436,7 @@ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059
>> >;
>> };
>>
>> - pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp {
>> + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grpgrp {
>
> s/grpgrp/grp?
>
>> fsl,pins = <
>> MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
>> MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
>> @@ -451,7 +451,7 @@ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130B9
>> >;
>> };
>>
>> - pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp {
>> + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grpgrp {
>
> Ditto
>
Indeed, Thanks. I'll check if I did not make same mistake in other places.
Best regards,
Krzysztof
