On Fri, Aug 30, 2024 at 01:42:10PM +0300, Dmitry Baryshkov wrote: > On Fri, Aug 23, 2024 at 10:04:15AM GMT, Abel Vesa wrote: > > The sixth PCIe instance on X1E80100 can be used in either 4-lane mode or > > 2-lane mode. Document the 4-lane mode as a separate compatible. > > As the patches were merged, it's too late for this series, but as a > note: we should think of a way to describe the PHY configuration without > changing the compatibility strings. The hardware stays the same, it's > just the number of lanes being wired that changes. No, this is not about configuration and we need two separate compatibles as the two PHY instances are distinct and only one of them can be used in 4-lane mode. The mistake was to ever describe pcie6a as 2-lane in the x1e80100 dtsi (and possibly also in the ambiguous commit message above). Whether pcie6a is used in 4-lane or 2-lane mode is determined by a TCSR register. Johan
