The AST2700 is the 7th generation SoC from Aspeed, featuring two GPIO
controllers: one with 12 GPIO pins and another with 216 GPIO pins.
Signed-off-by: Billy Tsai <billy_tsai@xxxxxxxxxxxxxx>
---
.../bindings/gpio/aspeed,ast2400-gpio.yaml | 46 ++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml
index cf11aa7ec8c7..4d439972c14b 100644
--- a/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/aspeed,ast2400-gpio.yaml
@@ -15,6 +15,7 @@ properties:
- aspeed,ast2400-gpio
- aspeed,ast2500-gpio
- aspeed,ast2600-gpio
+ - aspeed,ast2700-gpio
reg:
maxItems: 1
@@ -42,7 +43,7 @@ properties:
const: 2
ngpios:
- minimum: 36
+ minimum: 12
maximum: 232
required:
@@ -93,6 +94,20 @@ allOf:
enum: [ 36, 208 ]
required:
- ngpios
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: aspeed,ast2700-gpio
+ then:
+ properties:
+ gpio-line-names:
+ minItems: 12
+ maxItems: 216
+ ngpios:
+ enum: [ 12, 216 ]
+ required:
+ - ngpios
additionalProperties: false
@@ -146,3 +161,32 @@ examples:
gpio-ranges = <&pinctrl 0 208 36>;
ngpios = <36>;
};
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ gpio2: gpio@14c0b000 {
+ compatible = "aspeed,ast2700-gpio";
+ reg = <0x0 0x14c0b000 0x0 0x1000>;
+ interrupts-extended = <&soc1_intc2 18>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl1 0 0 216>;
+ ngpios = <216>;
+ };
+
+ gpio3: gpio@12c11000 {
+ compatible = "aspeed,ast2700-gpio";
+ reg = <0x0 0x12c11000 0x0 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl0 0 0 12>;
+ ngpios = <12>;
+ };
+ };
--
2.25.1
