Bindings expect pin configuration nodes in pinctrl to match certain
naming:
imx7s-colibri-eval-v3.dtb: pinctrl@30330000: 'lvdstx' does not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
imx7s-warp.dtb: pinctrl@30330000: 'usdhc3grp_100mhz', 'usdhc3grp_200mhz' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi | 2 +-
arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts | 4 ++--
arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi | 20 +++++++++----------
.../boot/dts/nxp/imx/imx7d-remarkable2.dts | 8 ++++----
arch/arm/boot/dts/nxp/imx/imx7s-warp.dts | 4 ++--
5 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
index 9fe51884af79..62e41edcaf1d 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
@@ -903,7 +903,7 @@ MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */
>;
};
- pinctrl_lvds_transceiver: lvdstx {
+ pinctrl_lvds_transceiver: lvdstxgrp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts
index 9c6476bda4a0..7ee66be8bccb 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts
@@ -419,7 +419,7 @@ &iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
- pinctrl_hog_1: hoggrp-1 {
+ pinctrl_hog_1: hoggrp {
fsl,pins = <
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d
@@ -665,7 +665,7 @@ &iomuxc_lpsr {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_2>;
- pinctrl_hog_2: hoggrp-2 {
+ pinctrl_hog_2: hoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x7d
MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi
index 8d5037ac03c7..a1574ccec89c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi
@@ -444,14 +444,14 @@ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
>;
};
- pinctrl_can1: can1frp {
+ pinctrl_can1: can1frpgrp {
fsl,pins = <
MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
>;
};
- pinctrl_can2: can2frp {
+ pinctrl_can2: can2frpgrp {
fsl,pins = <
MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
@@ -499,19 +499,19 @@ MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14
>;
};
- pinctrl_pwm1: pwm1 {
+ pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
>;
};
- pinctrl_pwm2: pwm2 {
+ pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
>;
};
- pinctrl_pwm3: pwm3 {
+ pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
>;
@@ -563,7 +563,7 @@ MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
>;
};
- pinctrl_usbotg1_pwr: usbotg_pwr {
+ pinctrl_usbotg1_pwr: usbotgpwrgrp {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
>;
@@ -581,7 +581,7 @@ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
@@ -593,7 +593,7 @@ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
@@ -631,7 +631,7 @@ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
@@ -646,7 +646,7 @@ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts
index 92cb45dacda6..eec526a96311 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts
@@ -508,7 +508,7 @@ MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
@@ -519,7 +519,7 @@ MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
@@ -546,7 +546,7 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
@@ -562,7 +562,7 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts
index 7bab113ca6da..af4acc311572 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts
@@ -459,7 +459,7 @@ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
@@ -475,7 +475,7 @@ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
--
2.43.0
