On Mon, Aug 05, 2024 at 01:42:51PM GMT, Eric Chanudet wrote: > assigned-clock sets DEV_RTIx_RTI_CLK(id:0) whereas clocks sets > DEV_RTIx_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT(id:1)[1]. This does not > look right, the timers in the driver assume a max frequency of 32kHz for > the heartbeat (HFOSC0 is 19.2MHz on j784s4-evm). > > With this change, WDIOC_GETTIMELEFT return coherent time left > (DEFAULT_HEARTBEAT=60, reports 60s upon opening the cdev). > > [1] http://downloads.ti.com/tisci/esd/latest/5_soc_doc/j784s4/clocks.html#clocks-for-rti0-device > > Fixes: caae599de8c6 ("arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances") > Suggested-by: Andrew Halaney <ahalaney@xxxxxxxxxx> > Signed-off-by: Eric Chanudet <echanude@xxxxxxxxxx> Tested-by: Andrew Halaney <ahalaney@xxxxxxxxxx> As mentioned throughout the other thread, you need the r5 u-boot build to configure the ESMs and the PMIC properly to get the board to actually reset (not in upstream u-boot at the moment). This patch fixes the watchdog itself though, prior timeleft was bogus etc but with this patch it starts at 60 sec (default) and reboots when we hit 0. Still an open question about the ESM(s) and their relationship with the PMIC, but that's an entirely independent subject to this fix. Thanks, Andrew
