Hi Geert,
Thank you for the review.
On Mon, Aug 26, 2024 at 11:38 AM Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Wed, Aug 21, 2024 at 10:56 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are
> > the list of blocks added:
> > - EXT CLKs
> > - 4X CA55
> > - SCIF
> > - PFC
> > - CPG
> > - SYS
> > - GIC
> > - ARMv8 Timer
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > ---
> > v2->v3
> > - Updated GIC node to match with the coding-style of DTS
>
> Thanks for the update!
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -0,0 +1,165 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/V2H(P) SoC
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + compatible = "renesas,r9a09g057";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + audio_extal_clk: audio-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
> > + };
> > +
> > + rtxin_clk: rtxin-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
> > + };
> > +
> > + qextal_clk: qextal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
> > + };
>
> Please use alphabetical sort order (by nodename).
>
Ok, I will sort this alphabetically.
> > + soc: soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + pinctrl: pinctrl@10410000 {
> > + compatible = "renesas,r9a09g057-pinctrl";
> > + reg = <0 0x10410000 0 0x10000>;
> > + clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-ranges = <&pinctrl 0 0 96>;
> > + #interrupt-cells = <2>;
> > + interrupt-controller;
> > + power-domains = <&cpg>;
> > + resets = <&cpg 165>, <&cpg 166>;
>
> Please use hexadecimal reset numbers, cfr. the description in the DT
> bindings. E.g. IOTOP_0_RESETN = CPG_RST_10 bit 5 => 0xa5.
>
> This comment applies to all resets in this series.
>
> > + };
>
> > + scif: serial@11c01400 {
> > + compatible = "renesas,scif-r9a09g057";
> > + reg = <0 0x11c01400 0 0x400>;
> > + interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "eri", "rxi", "txi", "bri", "dri",
> > + "tei", "tei-dri", "rxi-edge", "txi-edge";
> > + clocks = <&cpg CPG_MOD 143>;
>
> Please use hexadecimal module clock numbers, cfr. the description in
> the DT bindings. E.g. CGC_SCIF_0_clk_pck = CPG_CLKON_8 bit 15 => 0x8f.
>
> This comment applies to all module clocks in this series.
>
Ok, I will update the clock and reset numbers to use hexadecimal.
Cheers,
Prabhakar
