On Mon, Aug 26, 2024 at 11:53:56PM GMT, Kumar, Udit wrote: > Hello Eric > > On 8/21/2024 3:31 AM, Eric Chanudet wrote: > > On Mon, Aug 05, 2024 at 01:42:51PM GMT, Eric Chanudet wrote: > > > --- > > > I could not get the watchdog to do more than reporting 0x32 in > > > RTIWDSTATUS. Setting RTIWWDRXCTRL[0:3] to generate a reset instead of an > > > interrupt (0x5) didn't trigger a reset either when the window expired. > > Re-testing using u-boot from the BSP (2023.04) has the board reset as > > expected when the watchdog expires and WDIOC_GETTIMELEFT report the time > > left coherently with this patch until that happens. > > > > I initially had a u-boot with a DT lacking: > > "mcu_esm: esm@40800000" > > and I could reproduce the board not resetting by commenting in its > > description: > > "ti,esm-pins = <95>;" > > > > I don't understand why that is on the other hand. The TRM says ESM0 > > ERR_O drives the SOC_SAFETY_ERRORn pin, which goes to the PMIC GPIO3 on > > the schematic _and_ to MCU_ESM0 as an error input event. The tps6594-esm > > module is probing successfully and it sets both ESM_SOC_EN|ESM_SOC_ENDRV > > and ESM_SOC_START, so I would expect the PMIC to reset the board without > > MCU_ESM0 being described or configured by u-boot. > > AFAIK, Keerthy correct me. GPIO-7 of PMIC should reset the boards. That is what I'm seeing too, MCU_ESM0 is able to reset the board. > If you see figure 5-27 of TRM then SOC_SAFETY_ERRORn goes to GPIO-3 of > PMIC (schematic) > > Same time this is cascaded to MCU-ESM and WKUP-ESM to generate > MCU_SAFETY_ERRORn (from Wkup_ESM) > > and MCU_SAFETY_ERRORn is connected to GPIO-7. Agreed (Figure 5-25, in TRM "SPRUJ52" for J784S4). > Unlike other device J721E (for reference) > > SOC_SAFETY_ERRORn is generated by Main ESM and MCU_SAFETY_ERRORn can be > generated by WKUP_ESM and main_ESM. > > Please look at schematic of J721E SOM [0], both SOC_SAFETY_ERRZ and > MCU_SAFETY_ERRZ both are connected to GPIO-7 of PMIC. > > So on this device and board, only main ESM configuration is working for us. > > [0] https://www.ti.com/tool/J721EXSOMXEVM#tech-docs Sure, but I am using J784S4[1] and the schematic of that board (PROC141E4(001)_SCH) shows SOC_SAFETY_ERRZ going to PMIC GPIO3. So when u-boot _does not_ configure MCU_ESM0 chaining through pin95, I would still expect the board to reboot, because ESM0 raised SOC_SAFETY_ERRORn on TPS6594 GPIO3 which should reset the board. Yet that does not seem to happen. [1] https://www.ti.com/tool/J784S4XEVM#tech-docs On Mon, Aug 26, 2024 at 11:48:34AM GMT, Andrew Halaney wrote: > rti0 ---> ESM0 pin 688 --SOC_SAFETY_ERRORn--> TPS6594 GPIO3 > | > | > --> MCU_ESM0 pin 95 --> WKUP_ESM0 pin 63 --MCU_SAFETY_ERRORn--> TPS6584 GPIO7 Using Andrew's drawing as it matches my understanding as well. So the PMIC should reset the board even if MCU_ESM0 isn't configured with pin95 to chain SOC_SAFETY_ERRORn. Am I misunderstanding this? As well, since it is mentioned in Andrew's reply: On Mon, Aug 26, 2024 at 11:48:34AM GMT, Andrew Halaney wrote: > did you ensure that ESM0 was programmed in this test? Right now if > you're using upstream u-boot and upstream linux, nobody seems to be > configured by default to do that I am using the BSP u-boot (2023.04-f9b966c674) for this test, which has CONFIG_ESM_K3=y and esm@700000's description with pin688. Best, -- Eric Chanudet
