On Mon, Aug 26, 2024 at 12:38:36PM +0000, Harry Austen wrote: > Xilinx clocking wizard IP core supports monitoring of up to four > optional user clock inputs, with a corresponding interrupt for > notification in change of clock state (stop, underrun, overrun or > glitch). Give userspace access to this monitor logic through use of the > UIO framework. > > Implemented as an auxiliary_driver to avoid introducing UIO dependency > to the main clock driver. > > Signed-off-by: Harry Austen <hpausten@xxxxxxxxxxxxxx> > --- > drivers/uio/Kconfig | 8 ++++ > drivers/uio/Makefile | 1 + > drivers/uio/uio_xlnx_clk_mon.c | 71 ++++++++++++++++++++++++++++++++++ > 3 files changed, 80 insertions(+) > create mode 100644 drivers/uio/uio_xlnx_clk_mon.c > > diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig > index b060dcd7c6350..ca8a53de26a67 100644 > --- a/drivers/uio/Kconfig > +++ b/drivers/uio/Kconfig > @@ -164,4 +164,12 @@ config UIO_DFL > opae-sdk/tools/libopaeuio/ > > If you compile this as a module, it will be called uio_dfl. > + > +config UIO_XLNX_CLK_MON > + tristate "Xilinx user clock monitor support" > + depends on COMMON_CLK_XLNX_CLKWZRD > + help > + Userspace I/O interface to the user clock monitor logic within the > + Xilinx Clocking Wizard IP core. Why do you want a UIO api for a clock device? What userspace code is going to access the hardware this way? Why not use the normal kernel/user apis instead? thanks, greg k-h
