On Fri, 2024-08-23 at 10:01 +0200, Benjamin Hahn wrote: > Add support for the Mini PCIe slot. > > Signed-off-by: Benjamin Hahn <B.Hahn@xxxxxxxxx> Reviewed-by: Yannic Moog <y.moog@xxxxxxxxx> > --- > Changes in v3: > - change order of properties for pcie phy node > - Link to v2: > https://lore.kernel.org/r/20240821-wip-bhahn-add_pcie_support-v2-1-9c92d8488ab2@xxxxxxxxx > > Changes in v2: > - change pcie regulator to reg_vcc_3v3_sw > - add wake gpio to pcie pinctrl and order the gpios > - Link to v1: > https://lore.kernel.org/r/20240813-wip-bhahn-add_pcie_support-v1-1-c1bb062b4e1f@xxxxxxxxx > --- > .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 27 ++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > index 00a240484c25..bea479b5203a 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts > @@ -6,6 +6,7 @@ > > /dts-v1/; > > +#include <dt-bindings/phy/phy-imx8-pcie.h> > #include <dt-bindings/leds/leds-pca9532.h> > #include <dt-bindings/pwm/pwm.h> > #include "imx8mp-phycore-som.dtsi" > @@ -195,6 +196,23 @@ &snvs_pwrkey { > status = "okay"; > }; > > +&pcie_phy { > + clocks = <&hsio_blk_ctrl>; > + clock-names = "ref"; > + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; > + fsl,clkreq-unsupported; > + status = "okay"; > +}; > + > +/* Mini PCIe */ > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; > + vpcie-supply = <®_vcc_3v3_sw>; > + status = "okay"; > +}; > + > &pwm3 { > status = "okay"; > pinctrl-names = "default"; > @@ -366,6 +384,15 @@ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 > >; > }; > > + pinctrl_pcie0: pcie0grp { > + fsl,pins = < > + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 > + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60 > + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */ > + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 > + >; > + }; > + > pinctrl_pwm3: pwm3grp { > fsl,pins = < > MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 > > --- > base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba > change-id: 20240813-wip-bhahn-add_pcie_support-b9bd75fc4d98 > > Best regards,
