Hello Detlev,
Please see a comment below.
On 2024-08-22 23:15, Detlev Casanova wrote:
From: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
Some Rockchip devices put the phase settings into the dw_mmc
controller.
When the feature is present, the ciu-drive and ciu-sample clocks are
not used and the phase configuration is done directly through the mmc
controller.
Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
Signed-off-by: Detlev Casanova <detlev.casanova@xxxxxxxxxxxxx>
Acked-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
---
drivers/mmc/host/dw_mmc-rockchip.c | 171 +++++++++++++++++++++++++++--
1 file changed, 160 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c
b/drivers/mmc/host/dw_mmc-rockchip.c
index b07190ba4b7a..2748f9bf2691 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -15,7 +15,17 @@
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
-#define RK3288_CLKGEN_DIV 2
+#define RK3288_CLKGEN_DIV 2
+#define SDMMC_TIMING_CON0 0x130
+#define SDMMC_TIMING_CON1 0x134
+#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
+#define ROCKCHIP_MMC_DEGREE_MASK 0x3
+#define ROCKCHIP_MMC_DEGREE_OFFSET 1
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff <<
ROCKCHIP_MMC_DELAYNUM_OFFSET)
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
static const unsigned int freqs[] = { 100000, 200000, 300000, 400000
};
@@ -24,8 +34,143 @@ struct dw_mci_rockchip_priv_data {
struct clk *sample_clk;
int default_sample_phase;
int num_phases;
+ int internal_phase;
};
It might be good to declare internal_phase as "unsigned int
internal_phase:1",
i.e. as a bit field, which isn't going to save some memory in this
particular
case, but it would show additional attention to detail.
