reg = <0xc0 0x40018000 0x0 0x18000>; if you think it is more readable. > > > + #clock-cells = <1>; > > + clocks = <&clk_xosc>; > > + > > + assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>, > FWIW, I don't think any of these assigned clocks are helpful for the > example. That said, why do you need to configure all of these assigned > clocks via devicetree when this node is the provider of them? Not sure to understand what you mean here, the example is there just to show how to compile the dt node, maybe you're referring to the fact that the consumer should setup the clock freq? Consider that the rp1-clocks is coupled to the peripherals contained in the same RP1 chip so there is not much point in letting the peripherals set the clock to their leisure. > > > + <&rp1_clocks RP1_PLL_AUDIO_CORE>, > > + /* RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers */ > > Comments like this also do not seem relevant to the binding. Agreed, will drop in the next release. > > > Cheers, > Conor. > Many thanks, Andrea > > > + <&rp1_clocks RP1_PLL_SYS>, > > + <&rp1_clocks RP1_PLL_SYS_SEC>, > > + <&rp1_clocks RP1_PLL_AUDIO>, > > + <&rp1_clocks RP1_PLL_AUDIO_SEC>, > > + <&rp1_clocks RP1_CLK_SYS>, > > + <&rp1_clocks RP1_PLL_SYS_PRI_PH>, > > + /* RP1_CLK_SLOW_SYS is used for the frequency counter (FC0) */ > > + <&rp1_clocks RP1_CLK_SLOW_SYS>, > > + <&rp1_clocks RP1_CLK_SDIO_TIMER>, > > + <&rp1_clocks RP1_CLK_SDIO_ALT_SRC>, > > + <&rp1_clocks RP1_CLK_ETH_TSU>; > > + > > + assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE > > + <1536000000>, // RP1_PLL_AUDIO_CORE > > + <200000000>, // RP1_PLL_SYS > > + <125000000>, // RP1_PLL_SYS_SEC > > + <61440000>, // RP1_PLL_AUDIO > > + <192000000>, // RP1_PLL_AUDIO_SEC > > + <200000000>, // RP1_CLK_SYS > > + <100000000>, // RP1_PLL_SYS_PRI_PH > > + /* Must match the XOSC frequency */ > > + <50000000>, // RP1_CLK_SLOW_SYS > > + <1000000>, // RP1_CLK_SDIO_TIMER > > + <200000000>, // RP1_CLK_SDIO_ALT_SRC > > + <50000000>; // RP1_CLK_ETH_TSU > > + }; > > + }; > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 42decde38320..6e7db9bce278 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -19116,6 +19116,12 @@ F: Documentation/devicetree/bindings/media/raspberrypi,pispbe.yaml > > F: drivers/media/platform/raspberrypi/pisp_be/ > > F: include/uapi/linux/media/raspberrypi/ > > > > +RASPBERRY PI RP1 PCI DRIVER > > +M: Andrea della Porta <andrea.porta@xxxxxxxx> > > +S: Maintained > > +F: Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml > > +F: include/dt-bindings/clock/rp1.h > > + > > RC-CORE / LIRC FRAMEWORK > > M: Sean Young <sean@xxxxxxxx> > > L: linux-media@xxxxxxxxxxxxxxx > > diff --git a/include/dt-bindings/clock/rp1.h b/include/dt-bindings/clock/rp1.h > > new file mode 100644 > > index 000000000000..1ed67b8a5229 > > --- /dev/null > > +++ b/include/dt-bindings/clock/rp1.h > > @@ -0,0 +1,56 @@ > > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ > > +/* > > + * Copyright (C) 2021 Raspberry Pi Ltd. > > + */ > > + > > +#define RP1_PLL_SYS_CORE 0 > > +#define RP1_PLL_AUDIO_CORE 1 > > +#define RP1_PLL_VIDEO_CORE 2 > > + > > +#define RP1_PLL_SYS 3 > > +#define RP1_PLL_AUDIO 4 > > +#define RP1_PLL_VIDEO 5 > > + > > +#define RP1_PLL_SYS_PRI_PH 6 > > +#define RP1_PLL_SYS_SEC_PH 7 > > +#define RP1_PLL_AUDIO_PRI_PH 8 > > + > > +#define RP1_PLL_SYS_SEC 9 > > +#define RP1_PLL_AUDIO_SEC 10 > > +#define RP1_PLL_VIDEO_SEC 11 > > + > > +#define RP1_CLK_SYS 12 > > +#define RP1_CLK_SLOW_SYS 13 > > +#define RP1_CLK_DMA 14 > > +#define RP1_CLK_UART 15 > > +#define RP1_CLK_ETH 16 > > +#define RP1_CLK_PWM0 17 > > +#define RP1_CLK_PWM1 18 > > +#define RP1_CLK_AUDIO_IN 19 > > +#define RP1_CLK_AUDIO_OUT 20 > > +#define RP1_CLK_I2S 21 > > +#define RP1_CLK_MIPI0_CFG 22 > > +#define RP1_CLK_MIPI1_CFG 23 > > +#define RP1_CLK_PCIE_AUX 24 > > +#define RP1_CLK_USBH0_MICROFRAME 25 > > +#define RP1_CLK_USBH1_MICROFRAME 26 > > +#define RP1_CLK_USBH0_SUSPEND 27 > > +#define RP1_CLK_USBH1_SUSPEND 28 > > +#define RP1_CLK_ETH_TSU 29 > > +#define RP1_CLK_ADC 30 > > +#define RP1_CLK_SDIO_TIMER 31 > > +#define RP1_CLK_SDIO_ALT_SRC 32 > > +#define RP1_CLK_GP0 33 > > +#define RP1_CLK_GP1 34 > > +#define RP1_CLK_GP2 35 > > +#define RP1_CLK_GP3 36 > > +#define RP1_CLK_GP4 37 > > +#define RP1_CLK_GP5 38 > > +#define RP1_CLK_VEC 39 > > +#define RP1_CLK_DPI 40 > > +#define RP1_CLK_MIPI0_DPI 41 > > +#define RP1_CLK_MIPI1_DPI 42 > > + > > +/* Extra PLL output channels - RP1B0 only */ > > +#define RP1_PLL_VIDEO_PRI_PH 43 > > +#define RP1_PLL_AUDIO_TERN 44 > > -- > > 2.35.3 > >
