Re: [PATCH 06/13] media: qcom: camss: csiphy-3ph: Use an offset variable to find common control regs

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On 8/12/24 17:41, Depeng Shao wrote:
From: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>

New versions of the CSIPHY locate the control registers at offset 0x1000
not offset 0x800.

Provide a variable to base an offset from for the purposes of redirecting
the base offset for the new PHY regs layout.

The existing setup bases from 0x800, the new from 0x1000 with some of the
'EXT' registers dropped but the lower-order lane config regs at offset 0x00
and up the same as before.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
Signed-off-by: Depeng Shao <quic_depengs@xxxxxxxxxxx>
---
  .../qcom/camss/camss-csiphy-3ph-1-0.c         | 68 ++++++++++++-------
  1 file changed, 44 insertions(+), 24 deletions(-)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 93782ebfe0ea..1219a25ec55b 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -42,11 +42,11 @@
  #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n)	(0x03c + 0x100 * (n))
  #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL	0xb8
-#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n))
+#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n)	(offset + 0x4 * (n))

Macro value above shall be this one: ((offset) + 0x4 * (n))

  #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE	BIT(7)
  #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B	BIT(0)
  #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID	BIT(1)
-#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n)	(0x8b0 + 0x4 * (n))
+#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n)	((offset + 0xb0) + 0x4 * (n))

Macro value above shall be this one: ((offset) + 0xb0 + 0x4 * (n))

  #define CSIPHY_DEFAULT_PARAMS		0
  #define CSIPHY_LANE_ENABLE		1
@@ -66,6 +66,7 @@ struct csiphy_lane_regs {
  struct csiphy_device_regs {
  	const struct csiphy_lane_regs *lane_regs;
  	int lane_array_size;
+	u32 offset;
  };

With two minor fixes above,

Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>

--
Best wishes,
Vladimir




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