> > > The board should be designed such that the I2C bus pins of the SFP
> > > cage are connected to an I2C controller. There are also a few pins
> > > which ideally should be connected to GPIOs, LOS, Tx disable etc. You
> > > can then put a node in DT describing the SFP cage:
> > >
> > > Documentation/devicetree/bindings/net/sff,sfp.yaml
> > >
> > > sfp2: sfp {
> > > compatible = "sff,sfp";
> > > i2c-bus = <&sfp_i2c>;
> > > los-gpios = <&cps_gpio1 28 GPIO_ACTIVE_HIGH>;
> > > mod-def0-gpios = <&cps_gpio1 27 GPIO_ACTIVE_LOW>;
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&cps_sfpp0_pins>;
> > > tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
> > > tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
> > > };
> > >
> > > and then the ethernet node has a link to it:
> > >
> > > ethernet {
> > > phy-names = "comphy";
> > > phys = <&cps_comphy5 0>;
> > > sfp = <&sfp1>;
> > > };
> > >
> > > Phylink will then driver the SFP and tell the MAC what to do.
> >
> > I do not think the KSZ9477 switch design allows I2C access to the SFP
> > EEPROM.
>
> This is not a switch design issue, it is a board design issue. Plenty
> of Marvell switches have a PCR which do SGMII and 1000BaseX. Only the
> SFP SERDES data lines are connected to the switch. The I2C bus and
> other lines are connected to the SoC, not the switch.
>
> Do you have the schematics for the board you are testing on? Is it
> open? Can you give us a link?
My KSZ9477 board does not have that I2C connection, so I cannot
implement the change as suggested. I am getting a new design board that
needs verification of this connection. After I make it work I will
re-submit the patch.
Thanks for your help.
