On Mon, Aug 12, 2024 at 04:15:51PM +0200, Jan Kiszka wrote: > From: Jan Kiszka <jan.kiszka@xxxxxxxxxxx> > > Analogously to the PCI PHY, access to sys_syscon is needed to connect > the USB PHY to its controller. > > Signed-off-by: Jan Kiszka <jan.kiszka@xxxxxxxxxxx> > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx> > --- > CC: Rob Herring <robh@xxxxxxxxxx> > CC: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx> > CC: Conor Dooley <conor+dt@xxxxxxxxxx> > --- > .../bindings/phy/starfive,jh7110-usb-phy.yaml | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml > index 269e9f9f12b6..eaf0050c6f17 100644 > --- a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml > @@ -19,6 +19,16 @@ properties: > "#phy-cells": > const: 0 > > + starfive,sys-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to System Register Controller sys_syscon node. > + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. Why is having a new property for this required? The devicetree only has a single usb phy, so isn't it sufficient to look up the syscon by compatible, rather than via phandle + offset? > + description: > + The phandle to System Register Controller syscon node and the PHY connect offset > + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB controller. > + > clocks: > items: > - description: PHY 125m > @@ -47,4 +57,5 @@ examples: > <&stgcrg 6>; > clock-names = "125m", "app_125m"; > #phy-cells = <0>; > + starfive,sys-syscon = <&sys_syscon 0x18>; > }; > -- > 2.43.0 >
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