From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Add SDHI0-SDHI2 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> --- v1->v2 - New patch --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index c9e1e21b820d..435b1f4e7d38 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -429,6 +429,51 @@ gic: interrupt-controller@14900000 { <0x0 0x14940000 0 0x80000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + sdhi0: mmc@15c00000 { + compatible = "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c00000 0 0x10000>; + interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 163>, + <&cpg CPG_MOD 165>, + <&cpg CPG_MOD 164>, + <&cpg CPG_MOD 166>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 167>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@15c10000 { + compatible = "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c10000 0 0x10000>; + interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 167>, + <&cpg CPG_MOD 169>, + <&cpg CPG_MOD 168>, + <&cpg CPG_MOD 170>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 168>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi2: mmc@15c20000 { + compatible = "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c20000 0 0x10000>; + interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 171>, + <&cpg CPG_MOD 173>, + <&cpg CPG_MOD 172>, + <&cpg CPG_MOD 174>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 169>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { -- 2.34.1