On Tue, Jul 30, 2024 at 09:38:56AM +0530, Parthiban Veerasooran wrote: > Reset complete bit is set when the MAC-PHY reset completes and ready for > configuration. Additionally reset complete bit in the STS0 register has > to be written by one upon reset complete to clear the interrupt. > > Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@xxxxxxxxxxxxx> Reviewed-by: Andrew Lunn <andrew@xxxxxxx> Andrew