Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port
Bridge version 3.0.
Signed-off-by: Thippeswamy Havalige <thippesw@xxxxxxx>
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
---
.../bindings/pci/xlnx,xdma-host.yaml | 36 +++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
---
changes in v4
- update IP version
changes in v3
- constrain the new entry to only the new compatible.
- Remove example.
changes in v2
- update dt node label with pcie.
---
diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
index 2f59b3a73dd2..f1efd919c351 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
@@ -14,10 +14,21 @@ allOf:
properties:
compatible:
- const: xlnx,xdma-host-3.00
+ enum:
+ - xlnx,xdma-host-3.00
+ - xlnx,qdma-host-3.00
reg:
- maxItems: 1
+ items:
+ - description: configuration region and XDMA bridge register.
+ - description: QDMA bridge register.
+ minItems: 1
+
+ reg-names:
+ items:
+ - const: cfg
+ - const: breg
+ minItems: 1
ranges:
maxItems: 2
@@ -76,6 +87,27 @@ required:
- "#interrupt-cells"
- interrupt-controller
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,qdma-host-3.00
+then:
+ properties:
+ reg:
+ minItems: 2
+ reg-names:
+ minItems: 2
+ required:
+ - reg-names
+else:
+ properties:
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
unevaluatedProperties: false
examples:
--
2.34.1
