On 07/08/2024 13:20, Ivaylo Ivanov wrote:
>
> On 8/7/24 12:20, Krzysztof Kozlowski wrote:
>> On 07/08/2024 10:28, ivo.ivanov.ivanov1@xxxxxxxxx wrote:
>>> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
>>>
>>> Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy
>>> S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu
>>> 15 Plus (m1891). Add minimal support for that SoC, including:
>>>
>>> - All 8 cores via PSCI
>>> - ChipID
>>> - Generic ARMV8 Timer
>>> - Enumarate all pinctrl nodes
>>>
>>> Further platform support will be added over time.
>>>
>>> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
>>> ---
>>> .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++
>>> arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++
>>> 2 files changed, 1631 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi
>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi
>>> new file mode 100644
>>> index 000000000..1dcb61e2e
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi
>>> @@ -0,0 +1,1378 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source
>>> + *
>>> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include "exynos-pinctrl.h"
>>> +
>>> +&pinctrl_alive {
>>> + gpa0: gpa0 {
>> I do not believe this was tested. See maintainer SoC profile for Samsung
>> Exynos.
>>
>> Limited review follows due to lack of testing.
>>
>>
>>> +};
>>> diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi
>>> new file mode 100644
>>> index 000000000..3ed381ee5
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi
>>> @@ -0,0 +1,253 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Samsung's Exynos 8895 SoC device tree source
>>> + *
>>> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> + compatible = "samsung,exynos8895";
>>> + #address-cells = <2>;
>>> + #size-cells = <1>;
>>> +
>>> + interrupt-parent = <&gic>;
>>> +
>>> + aliases {
>>> + pinctrl0 = &pinctrl_alive;
>>> + pinctrl1 = &pinctrl_abox;
>>> + pinctrl2 = &pinctrl_vts;
>>> + pinctrl3 = &pinctrl_fsys0;
>>> + pinctrl4 = &pinctrl_fsys1;
>>> + pinctrl5 = &pinctrl_busc;
>>> + pinctrl6 = &pinctrl_peric0;
>>> + pinctrl7 = &pinctrl_peric1;
>>> + };
>>> +
>>> + arm-a53-pmu {
>> Are there two pmus?
>
> Hm. The Downstream kernel has them all under one node with compatible
>
> 'arm,armv8-pmuv3', same as with Exynos 7885. So it should have two PMUs,
>
> one for each cluster.
>
>
> Considering the second cluster consists of Samsung's custom Mongoose M2
>
> cores, what would be the most adequate thing to do? Keep the first PMU as
>
> "arm,cortex-a53-pmu" and use the SW model "arm,armv8-pmuv3" for the
>
> second PMU? I doubt guessing if these mongoose cores are based on already
>
> existing cortex cores is a great idea.
I was just wondering why there is only one and called a53. I am not sure
what should be for the second, but rather not a software model.
Best regards,
Krzysztof
