On 16:34-20240720, Siddharth Vadapalli wrote:
> The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4
> lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM
> via SERDES1. Since SERDES1 is not being used by any peripheral apart
> from PCIe0, use all 4 lanes of SERDES1 for PCIe0.
>
> Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode")
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
> ---
>
> Hello,
>
> This patch is based on linux-next tagged next-20240715.
> Patch has been tested on J784S4-EVM. Logs:
> https://gist.github.com/Siddharth-Vadapalli-at-TI/2b9b1196ff6b9eac895a7986e5ff4456
> NOTE: Patch applies cleanly on Mainline Linux's latest commit
> 3c3ff7be9729 Merge tag 'powerpc-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
>
> Regards,
> Siddharth.
>
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index ffa38f41679d..ea27519d7b89 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -1407,10 +1407,11 @@ &serdes1 {
>
> serdes1_pcie0_link: phy@0 {
> reg = <0>;
> - cdns,num-lanes = <2>;
> + cdns,num-lanes = <4>;
> #phy-cells = <0>;
> cdns,phy-type = <PHY_TYPE_PCIE>;
> - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
> + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>,
> + <&serdes_wiz1 3>, <&serdes_wiz1 4>;
> };
OK - I see the reason why
https://lore.kernel.org/all/20240807132054.jcz5fdokc5yk3mbo@entrust/
was missed.
Please sync with Manorit to make sure we sequence these correctly -
looks to me that this fixup needs to get in first? have you also checked
up on AM69-SK ?
> };
>
> --
> 2.40.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
