On 07/08/2024 08:40, Xianwei Zhao wrote:
> Hi Krzysztof,
> Thank you for your reply.
>
> On 2024/8/7 13:44, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 07/08/2024 03:55, Xianwei Zhao wrote:
>>> Hi Krzysztof,
>>> Thanks for your review.
>>>
>>> On 2024/8/6 21:10, Krzysztof Kozlowski wrote:
>>>> [ EXTERNAL EMAIL ]
>>>>
>>>> On 06/08/2024 12:27, Xianwei Zhao via B4 Relay wrote:
>>>>> From: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
>>>>>
>>>>> Add C3 PLL controller input clock parameters "fix".
>>>>
>>>> What is "parameters" here? Why you are adding it? Is it missing?
>>>> Something is not working?
>>>>
>>> Yes. The previous submission was lost.
>>
>> What submission is lost?
>>
>>>
>>>>>
>>>>> Fixes: 0e6be855a96d ("dt-bindings: clock: add Amlogic C3 PLL clock controller")
>>>>
>>>> Why? What bug are you fixing?
>>>
>>> The input clock of PLL clock controller need the clock whose fw_name is
>>> called "fix".
>>
>> Then explain this in commit msg.
>>
> Will add this in commit msg.
>>>>
>>>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
>>>>> ---
>>>>> Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml | 7 +++++--
>>>>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>>>>> index 43de3c6fc1cf..700865cc9792 100644
>>>>> --- a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
>>>>> @@ -24,11 +24,13 @@ properties:
>>>>> items:
>>>>> - description: input top pll
>>>>> - description: input mclk pll
>>>>> + - description: input fix pll
>>>>>
>>>>> clock-names:
>>>>> items:
>>>>> - const: top
>>>>> - const: mclk
>>>>> + - const: fix
>>>>
>>>> and that's not an ABI break because?
>>> This is "fixed" clock.
>>> I will modify "fix" to "fixed",in next version.
>>
>> With "fixed" it is still ABI break, right?
>> No. The clock named "fixed" was initially implemented in the PLL clock
> controller driver, but some registers needed secure zone access,
> so we put it in secure zone(BL31) implemented and access it through the
> SCMI. but the PLL clock driver need uses this clock, so the "fixed"
> clock is input as an input source,
> We changed the driver and forgot to change the binding, so we added it here.
Fix your quoting or your email program - I don't understand what you are
saying here.
Anyway, provide justification in the commit msg.
Best regards,
Krzysztof
