Hi Krzysztof,
Thanks for your reply.
On 2024/8/6 21:13, Krzysztof Kozlowski wrote:
[ EXTERNAL EMAIL ]
On 06/08/2024 12:27, Xianwei Zhao via B4 Relay wrote:
From: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
Add some device nodes for SoC C3, including periphs clock controller
node, PLL clock controller node, SPICC node, regulator node, NAND
controller node, sdcard node, Ethernet MAC and PHY node.
Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
---
.../boot/dts/amlogic/amlogic-c3-c302x-aw409.dts | 249 +++++++++++
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 487 ++++++++++++++++++++-
2 files changed, 735 insertions(+), 1 deletion(-)
...
+
+ sd: mmc@8a000 {
+ compatible = "amlogic,meson-axg-mmc";
+ reg = <0x0 0x8a000 0x0 0x800>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&pwrc PWRC_C3_SDCARD_ID>;
+ clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
+ <&clkc_periphs CLKID_SD_EMMC_B>,
+ <&clkc_pll CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ no-mmc;
+ no-sdio;
Hm? Why are these blocks incomplete that they do not handle SDIO? Aren't
you putting board properties into SoC?
The sdacrd (mmc@8a000) depends on regulator and pinctrl(select), So some
property fields are placed at the board level. The SDIO is connect with
the firmware (wifi&bt). Now I'll remove SDIO implementation and wait
until later to submit it with the firmware.
Best regards,
Krzysztof
