On 04/08/2024 23:53, David Virag wrote:
> Add USB controller and USB PHY controller nodes to Exynos7885 SoC DTSI
>
> The SoC theoretically supports USB3 SuperSpeed, but is not implemented
> in any known device. The vendor kernel also stubs out USB3 functions, so
> we do not support it.
>
> It is though, perfectly capable of USB 2.0 high-speed mode, both as host
> and device.
>
> Signed-off-by: David Virag <virag.david003@xxxxxxxxx>
> ---
> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 35 ++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> index 008228fb319a..1352c64d132e 100644
> --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> @@ -463,6 +463,41 @@ i2c_7: i2c@11cd0000 {
> clock-names = "i2c";
> status = "disabled";
> };
> +
> + usbdrd: usb@13600000 {
> + compatible = "samsung,exynos7885-dwusb3";
> + ranges = <0x0 0x13600000 0x10000>;
> + clocks = <&cmu_fsys CLK_FSYS_USB30DRD_BUS_CLK_EARLY>,
> + <&cmu_fsys CLK_FSYS_USB30DRD_REF_CLK>;
> + clock-names = "bus_early", "ref";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + status = "disabled";
> +
> + usbdrd_dwc3: usb@0 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x10000>;
> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&usbdrd_phy 0>;
> + phy-names = "usb2-phy";
> + /*
> + * SoC in theory supports SS but no device has it.
> + * Actual capabilities unknown.
> + */
> + maximum-speed = "high-speed";
> + };
> + };
> +
> + usbdrd_phy: phy@135d0000 {
Keep the nodes ordered by unit address.
Best regards,
Krzysztof
