On 03/08/2024 12:58, Harry Austen wrote: > This Xilinx clocking wizard IP core outputs this interrupt signal to > indicate when one of the four optional user clock inputs is either > stopped, overruns, underruns or glitches. > > This functionality was only added from version 6.0 onwards, so restrict > it to particular compatible strings. > > Signed-off-by: Harry Austen <hpausten@xxxxxxxxxxxxxx> > --- > v1 -> v2: Fix binding errors by moving interrupts up front, restrict later > > .../bindings/clock/xlnx,clocking-wizard.yaml | 25 ++++++++++++++++++- > 1 file changed, 24 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > index 9d5324dc1027a..9e5078cef2962 100644 > --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > @@ -39,6 +39,14 @@ properties: > - const: clk_in1 > - const: s_axi_aclk > > + interrupts: > + items: > + - description: user clock monitor interrupt > + > + interrupt-names: > + items: > + - const: monitor > + > Why multiple blank lines? Only one. > xlnx,speed-grade: > $ref: /schemas/types.yaml#/definitions/uint32 > @@ -62,17 +70,32 @@ required: > - xlnx,speed-grade > - xlnx,nr-outputs With above fixed: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
