On 31/07/2024 03:43, Hui-Ping Chen wrote:
> Nuvoton MA35 SoCs support DWC2 USB controller.
> Add the driver to drive the USB 2.0 PHY transceivers.
>
> Signed-off-by: Hui-Ping Chen <hpchen0nvt@xxxxxxxxx>
> +struct ma35_usb_phy {
> + struct clk *clk;
> + struct device *dev;
> + struct regmap *sysreg;
> +};
> +
> +static int ma35_usb_phy_power_on(struct phy *phy)
> +{
> + struct ma35_usb_phy *p_phy = phy_get_drvdata(phy);
> + unsigned int val;
> + int ret;
> +
> + ret = clk_prepare_enable(p_phy->clk);
> + if (ret < 0) {
> + dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
> + return ret;
> + }
> +
> + regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
> + if (val & PHY0SUSPEND) {
> + /*
> + * USB PHY0 is in operation mode already
> + * make sure USB PHY 60 MHz UTMI Interface Clock ready
> + */
> + ret = readl_poll_timeout((void __iomem *)p_phy->sysreg + MA35_SYS_REG_USBPMISCR,
sysreg is a regmap, not io address. How could it possibly work and be
tested?!? This cannot work. Test your code *before* sending it.
> + val, val & PHY0DEVCKSTB, 1, 100);
> + if (ret == -ETIMEDOUT) {
> + dev_err(p_phy->dev, "1.Check PHY clock, Timeout: %d\n", val);
> + return ret;
> + }
> + return 0;
> + }
> +
> + /*
> + * reset USB PHY0.
> + * wait until USB PHY0 60 MHz UTMI Interface Clock ready
> + */
> + regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, (PHY0POR | PHY0SUSPEND));
> + udelay(10);
> +
> + /* make USB PHY0 enter operation mode */
> + regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, PHY0SUSPEND);
> +
> + /* make sure USB PHY 60 MHz UTMI Interface Clock ready */
> + ret = readl_poll_timeout((void __iomem *)p_phy->sysreg + MA35_SYS_REG_USBPMISCR,
Same problem.
Best regards,
Krzysztof
