k3-j784s4-j742s2-common.dtsi will be included in k3-j742s2.dtsi at a
later point so move j784s4 related stuff to k3-j784s4.dtsi
Signed-off-by: Manorit Chawdhry <m-chawdhry@xxxxxx>
---
.../arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 156 --------------------
arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 158 +++++++++++++++++++++
2 files changed, 158 insertions(+), 156 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
index 76e43ee44496..958054ab1018 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
@@ -15,166 +15,10 @@
#include "k3-pinctrl.h"
/ {
- model = "Texas Instruments K3 J784S4 SoC";
- compatible = "ti,j784s4";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu-map {
- cluster0: cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
-
- core2 {
- cpu = <&cpu2>;
- };
-
- core3 {
- cpu = <&cpu3>;
- };
- };
-
- cluster1: cluster1 {
- core0 {
- cpu = <&cpu4>;
- };
-
- core1 {
- cpu = <&cpu5>;
- };
-
- core2 {
- cpu = <&cpu6>;
- };
-
- core3 {
- cpu = <&cpu7>;
- };
- };
- };
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a72";
- reg = <0x000>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a72";
- reg = <0x001>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a72";
- reg = <0x002>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
-
- cpu3: cpu@3 {
- compatible = "arm,cortex-a72";
- reg = <0x003>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_0>;
- };
-
- cpu4: cpu@100 {
- compatible = "arm,cortex-a72";
- reg = <0x100>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_1>;
- };
-
- cpu5: cpu@101 {
- compatible = "arm,cortex-a72";
- reg = <0x101>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_1>;
- };
-
- cpu6: cpu@102 {
- compatible = "arm,cortex-a72";
- reg = <0x102>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_1>;
- };
-
- cpu7: cpu@103 {
- compatible = "arm,cortex-a72";
- reg = <0x103>;
- device_type = "cpu";
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- next-level-cache = <&L2_1>;
- };
- };
-
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
index 46cff5ed3730..16ade4fd9cbd 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
@@ -10,3 +10,161 @@
#include "k3-j784s4-j742s2-common.dtsi"
+/ {
+ model = "Texas Instruments K3 J784S4 SoC";
+ compatible = "ti,j784s4";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1: cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a72";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a72";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a72";
+ reg = <0x002>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a72";
+ reg = <0x003>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,cortex-a72";
+ reg = <0x102>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,cortex-a72";
+ reg = <0x103>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+ };
+};
--
2.45.1
