On Wed, Jul 31, 2024 at 09:23:54AM GMT, Alexandre Ghiti wrote: > riscv does not have lr instructions on byte and halfword but the > qspinlock implementation actually uses such atomics provided by the > Zabha extension, so those sizes are legitimate. We currently always come to __cmpwait() through smp_cond_load_relaxed() and queued_spin_lock_slowpath() adds another invocation. However, isn't the reason we're hitting the BUILD_BUG() because the switch fails to find a case for 16, not because it fails to find cases for 1 or 2? The new invocation passes a pointer to a struct mcs_spinlock, which looks like it has size 16. We need to ensure that when ptr points to a pointer that we pass the size of uintptr_t. > > Then instead of failing to build, just fallback to the !Zawrs path. No matter what sizes we're failing on, if we do this then queued_spin_lock_slowpath() won't be able to take advantage of Zawrs. Thanks, drew > > Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> > --- > arch/riscv/include/asm/cmpxchg.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index ebbce134917c..9ba497ea18a5 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -268,7 +268,8 @@ static __always_inline void __cmpwait(volatile void *ptr, > break; > #endif > default: > - BUILD_BUG(); > + /* RISC-V doesn't have lr instructions on byte and half-word. */ > + goto no_zawrs; > } > > return; > -- > 2.39.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
