Add missing pinctrl settings for PCIe 3.0 x1 clock request and wake
signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Rename node from 'pcie2' to 'pcie30x1' to align with schematic
nomenclature.
Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
number.
V3: New patch.
---
.../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 1c7080cca11f..eeae14842b71 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -318,7 +318,7 @@ map2 {
&pcie2x1l0 {
pinctrl-names = "default";
- pinctrl-0 = <&pcie2_0_rst>;
+ pinctrl-0 = <&pcie30x1_pins>;
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
status = "okay";
@@ -364,16 +364,24 @@ hp_detect: hp-detect {
};
pcie2 {
- pcie2_0_rst: pcie2-0-rst {
- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ pcie2_2_rst: pcie2-2-rst {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ };
+ pcie30x1 {
pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
- pcie2_2_rst: pcie2-2-rst {
- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ pcie30x1_pins: pcie30x1-pins {
+ rockchip,pins =
+ /* PCIE30x1_0_CLKREQn_M1_L */
+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>,
+ /* PCIE30x1_0_PERSTn_M1_L */
+ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>,
+ /* PCIE30x1_0_WAKEn_M1_L */
+ <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
--
2.44.0
