Add Densitron DMT028VGHMCMI-1D 480x640 TFT matrix 2.83 inch panel
attached to Ilitek ILI9806E DSI TCON into the ILI9806E driver.
Note that the Densitron panels use different TCONs, this driver is for
the later panel, use panel-ilitek-st7701.c for the former panel:
DMT028VGHMCMI-1A - ST7701
DMT028VGHMCMI-1D - ILI9806E
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: Daniel Vetter <daniel@xxxxxxxx>
Cc: David Airlie <airlied@xxxxxxxxx>
Cc: Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>
Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
Cc: Maxime Ripard <mripard@xxxxxxxxxx>
Cc: Michael Walle <mwalle@xxxxxxxxxx>
Cc: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Cc: Thomas Zimmermann <tzimmermann@xxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
---
drivers/gpu/drm/panel/panel-ilitek-ili9806e.c | 165 ++++++++++++++++++
1 file changed, 165 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c
index e4a44cd26c4dc..a3c79ad99d0bd 100644
--- a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c
@@ -380,7 +380,172 @@ static const struct panel_desc com35h3p70ulc_desc = {
.lanes = 2,
};
+static void dmt028vghmcmi_1d_init(struct mipi_dsi_multi_context *ctx)
+{
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x10);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x06);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x07);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x16);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x83);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x89);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0x8a);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x44);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x44);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x78);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x78);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x6c);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x6c);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00);
+ /* Gamma settings */
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x09);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x14);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x09);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x05);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x07);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x07);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x08);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x0c);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x05);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x19);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x00);
+
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x14);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x11);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x05);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0c);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x08);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x03);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x06);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x10);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x05);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0d);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x15);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x13);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x00);
+
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x22);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x77);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xe1, 0x79);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x13);
+
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06);
+ /* GIP 0 */
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x21);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x05);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x98);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x06);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0xf7);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xf0);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0xc0);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x08);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00);
+ /* GIP 1 */
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x44);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67);
+ /* GIP 2 */
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x01);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0xbc);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xad);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xda);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xcb);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x55);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x76);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x67);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x88);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x11);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22);
+
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x10);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x10);
+ mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x13);
+
+ mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00);
+};
+
+static const struct drm_display_mode dmt028vghmcmi_1d_default_mode = {
+ .clock = 22000,
+
+ .hdisplay = 480,
+ .hsync_start = 480 + 20,
+ .hsync_end = 480 + 20 + 4,
+ .htotal = 480 + 20 + 4 + 10,
+
+ .vdisplay = 640,
+ .vsync_start = 640 + 40,
+ .vsync_end = 640 + 40 + 4,
+ .vtotal = 640 + 40 + 4 + 20,
+
+ .width_mm = 53,
+ .height_mm = 79,
+
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc dmt028vghmcmi_1d_desc = {
+ .init_sequence = dmt028vghmcmi_1d_init,
+ .display_mode = &dmt028vghmcmi_1d_default_mode,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .format = MIPI_DSI_FMT_RGB888,
+ .lanes = 2,
+};
+
static const struct of_device_id ili9806e_of_match[] = {
+ { .compatible = "densitron,dmt028vghmcmi-1d", .data = &dmt028vghmcmi_1d_desc },
{ .compatible = "ortustech,com35h3p70ulc", .data = &com35h3p70ulc_desc },
{ }
};
--
2.43.0
