On Mon, Jul 22, 2024 at 11:41:18AM +0200, ysionneau@xxxxxxxxxxxxx wrote: > From: Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > > Add binding for Kalray Coolidge IPI controller. > > Co-developed-by: Jules Maselbas <jmaselbas@xxxxxxxx> > Signed-off-by: Jules Maselbas <jmaselbas@xxxxxxxx> > Signed-off-by: Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > --- > > Notes: > > V2 -> V3: > - fixed bindings to adhere to dt-schema > - moved to interrupt-controller directory, like the related driver > --- > .../kalray,coolidge-ipi-ctrl.yaml | 79 +++++++++++++++++++ > 1 file changed, 79 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml > new file mode 100644 > index 0000000000000..91e3afe4f1ca5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml > @@ -0,0 +1,79 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-ipi-ctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Kalray Coolidge SoC Inter-Processor Interrupt Controller (IPI) > + > +maintainers: > + - Jonathan Borne <jborne@xxxxxxxxxxxxx> > + - Julian Vetter <jvetter@xxxxxxxxxxxxx> > + - Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > + > +description: | > + The Inter-Processor Interrupt Controller (IPI) provides a fast synchronization > + mechanism to the software. It exposes eight independent set of registers that > + can be use to notify each processor in the cluster. > + A set of registers contains two 32-bit registers: > + - 17-bit interrupt control, one bit per core, raise an interrupt on write > + - 17-bit mask, one per core, to enable interrupts > + > + Bit at offsets 0 to 15 selects cores in the cluster, respectively PE0 to PE15, > + while bit at offset 16 is for the cluster Resource Manager (RM) core. > + > + The eight output interrupts are connected to each processor core interrupt > + controller (intc). It says there are 16 interrupt outputs below... > + > +properties: > + compatible: > + const: kalray,coolidge-ipi-ctrl > + > + reg: > + maxItems: 1 > + > + interrupts-extended: > + maxItems: 16 > + description: | > + Specifies the interrupt line the IPI controller will raise on the core INTC. > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 0 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + - interrupt-controller > + - '#interrupt-cells' > + > +examples: > + - | > + ipi: inter-processor-interrupt@ad0000 { > + compatible = "kalray,coolidge-ipi-ctrl"; > + reg = <0x00 0xad0000 0x00 0x1000>; > + #interrupt-cells = <0>; > + interrupt-controller; > + interrupts-extended = <&core_intc0 24>, > + <&core_intc1 24>, > + <&core_intc2 24>, > + <&core_intc3 24>, > + <&core_intc4 24>, > + <&core_intc5 24>, > + <&core_intc6 24>, > + <&core_intc7 24>, > + <&core_intc8 24>, > + <&core_intc9 24>, > + <&core_intc10 24>, > + <&core_intc11 24>, > + <&core_intc12 24>, > + <&core_intc13 24>, > + <&core_intc14 24>, > + <&core_intc15 24>; > + }; > + > +... > -- > 2.45.2 > > > > >
