On Mon, Jul 22, 2024 at 11:41:16AM +0200, ysionneau@xxxxxxxxxxxxx wrote: > From: Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > > Add binding for Kalray Coolidge APIC Mailbox interrupt-controller. > > Co-developed-by: Jules Maselbas <jmaselbas@xxxxxxxx> > Signed-off-by: Jules Maselbas <jmaselbas@xxxxxxxx> > Signed-off-by: Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > --- > > Notes: > > V2 -> V3: Fixed bindings to adhere to dt-schema > --- > .../kalray,coolidge-apic-mailbox.yaml | 90 +++++++++++++++++++ > 1 file changed, 90 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml > new file mode 100644 > index 0000000000000..334b816b80583 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-mailbox.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-mailbox.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Kalray Coolidge APIC-Mailbox > + > +maintainers: > + - Jonathan Borne <jborne@xxxxxxxxxxxxx> > + - Julian Vetter <jvetter@xxxxxxxxxxxxx> > + - Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > + > +description: | > + Each cluster in the Coolidge SoC includes an Advanced Programmable Interrupt > + Controller (APIC) which is split in two part: > + - a Generic Interrupt Controller (referred as APIC-GIC) > + - a Mailbox Controller (referred as APIC-Mailbox) > + The APIC-Mailbox contains 128 mailboxes of 8 bytes (size of a word), > + this hardware block is basically a 1 KB of smart memory space. > + Each mailbox can be independently configured with a trigger condition > + and an input mode function. > + > + Input mode are: > + - write > + - bitwise OR > + - add > + > + Interrupts are generated on a write when the mailbox content value > + match the configured trigger condition. > + Available conditions are: > + - doorbell: always raise interruption on write > + - match: when the mailbox's value equal the configured trigger value > + - barrier: same as match but the mailbox's value is cleared on trigger > + - threshold: when the mailbox's value is greater than, or equal to, the > + configured trigger value > + > + Since this hardware block generates IRQs based on writes to some memory > + locations, it is both an interrupt controller and an MSI controller. > + > +properties: > + compatible: > + const: kalray,coolidge-apic-mailbox > + > + reg: > + maxItems: 1 > + > + "#interrupt-cells": > + const: 0 > + description: > + The IRQ number. > + > + "#address-cells": > + const: 0 > + > + interrupt-controller: true > + > + interrupts: > + maxItems: 128 > + minItems: 1 > + description: | > + Specifies the interrupt line(s) in the interrupt-parent controller node; > + valid values depend on the type of parent interrupt controller Your description applies to all 'interrupts' properties and is therefore redundant. What you should explain is what are the 1-128 possible interrupts. Normally, you have to list each one out unless they are all instances of the same type of interrupt. > + > + msi-controller: true "#msi-cells" should be specified too. > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - "#interrupt-cells" > + - "#address-cells" > + - interrupt-controller > + - interrupts > + - msi-controller > + > +examples: > + - | > + apic_mailbox: interrupt-controller@a00000 { > + compatible = "kalray,coolidge-apic-mailbox"; > + reg = <0 0xa00000 0 0x0f200>; > + #interrupt-cells = <0>; > + interrupt-controller; > + interrupt-parent = <&apic_gic>; > + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>; > + msi-controller; > + }; > + > +... > -- > 2.45.2 > > > > >
