On 7/17/2024 2:08 PM, Manivannan Sadhasivam wrote:
On Tue, Jul 16, 2024 at 02:53:47PM +0530, Sricharan R wrote:
From: devi priya <quic_devipriy@xxxxxxxxxxx>
The IPQ9574 platform has four Gen3 PCIe controllers:
two single-lane and two dual-lane based on SNPS core 5.70a.
QCOM IP rev is 1.27.0 and Synopsys IP rev is 5.80a.
Add a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0'
which reuses all the members of 'ops_2_9_0' except for the
post_init as the SLV_ADDR_SPACE_SIZE configuration differs
between 2_9_0 and 1_27_0.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
Co-developed-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
Signed-off-by: Anusha Rao <quic_anusha@xxxxxxxxxxx>
Signed-off-by: devi priya <quic_devipriy@xxxxxxxxxxx>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
---
[V6] Fixed all Manivannan's and Bjorn Helgaas comments.
Removed the SLV_ADDR_SPACE_SZ_1_27_0 macro to have default value.
drivers/pci/controller/dwc/pcie-qcom.c | 31 ++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 0180edf3310e..26acd9f5385e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1116,16 +1116,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
return clk_bulk_prepare_enable(res->num_clks, res->clks);
}
-static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
+static int qcom_pcie_post_init(struct qcom_pcie *pcie)
{
struct dw_pcie *pci = pcie->pci;
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u32 val;
int i;
- writel(SLV_ADDR_SPACE_SZ,
- pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
-
val = readl(pcie->parf + PARF_PHY_CTRL);
val &= ~PHY_TEST_PWR_DOWN;
writel(val, pcie->parf + PARF_PHY_CTRL);
@@ -1165,6 +1162,18 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
return 0;
}
+static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
+{
+ return qcom_pcie_post_init(pcie);
+}
+
+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
+{
+ writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
+
As discussed in [1], DBI/ATU mirroring should be disabled completely to avoid
the enumeration issue you are seeing on this platform. Please rebase on top of
the referenced patch (once v2 gets posted).
ok, got it.
Regards,
Sricharan
