On 15/07/2024 11:36, Satya Priya Kakitapalli (Temp) wrote:
This clock is PoR ON clock and expected to be always enabled from HW perspective, we are just re-ensuring it is ON from probe. Modelling this clock is unnecessary, and we have been following this approach for gdsc clock in all the recent chipsets, like for example sm8550 camcc.
Having a difficult time following the logic - Re-enabling an already enabled always-on clock is necessary - Modelling the always-on clock in the CCF to park it at XO is unnecessary I think that's a pretty vague argument to be honest. --- bod
