Convert the bindings for the Qualcomm EMAC Ethernet Controller from the old text format to yaml. Also move the phy node of the controller to be within an mdio block so we can use mdio.yaml. Signed-off-by: Rayyan Ansari <rayyan.ansari@xxxxxxxxxx> --- .../devicetree/bindings/net/qcom,emac.yaml | 98 ++++++++++++++++ .../devicetree/bindings/net/qcom-emac.txt | 111 ------------------ 2 files changed, 98 insertions(+), 111 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/qcom,emac.yaml delete mode 100644 Documentation/devicetree/bindings/net/qcom-emac.txt diff --git a/Documentation/devicetree/bindings/net/qcom,emac.yaml b/Documentation/devicetree/bindings/net/qcom,emac.yaml new file mode 100644 index 000000000000..cef65130578f --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,emac.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +--- +$id: http://devicetree.org/schemas/net/qcom,emac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm EMAC Gigabit Ethernet Controller + +maintainers: + - Timur Tabi <timur@xxxxxxxxxx> + +properties: + compatible: + oneOf: + - const: qcom,fsm9900-emac + - enum: + - qcom,fsm9900-emac-sgmii + - qcom,qdf2432-emac-sgmii + reg: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +if: + properties: + compatible: + const: qcom,fsm9900-emac +then: + allOf: + - $ref: ethernet-controller.yaml# + properties: + clocks: + minItems: 7 + maxItems: 7 + + clock-names: + items: + - const: axi_clk + - const: cfg_ahb_clk + - const: high_speed_clk + - const: mdio_clk + - const: tx_clk + - const: rx_clk + - const: sys_clk + + internal-phy: + maxItems: 1 + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + + required: + - clocks + - clock-names + - internal-phy + - phy-handle + - mdio + +unevaluatedProperties: false + +examples: + - | + emac0: ethernet@feb20000 { + compatible = "qcom,fsm9900-emac"; + reg = <0xfeb20000 0x10000>, + <0xfeb36000 0x1000>; + interrupts = <76>; + + clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, + <&gcc 6>, <&gcc 7>; + clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", + "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; + + internal-phy = <&emac_sgmii>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + emac_sgmii: ethernet@feb38000 { + compatible = "qcom,fsm9900-emac-sgmii"; + reg = <0xfeb38000 0x1000>; + interrupts = <80>; + }; diff --git a/Documentation/devicetree/bindings/net/qcom-emac.txt b/Documentation/devicetree/bindings/net/qcom-emac.txt deleted file mode 100644 index 7ae8aa148634..000000000000 --- a/Documentation/devicetree/bindings/net/qcom-emac.txt +++ /dev/null @@ -1,111 +0,0 @@ -Qualcomm Technologies EMAC Gigabit Ethernet Controller - -This network controller consists of two devices: a MAC and an SGMII -internal PHY. Each device is represented by a device tree node. A phandle -connects the MAC node to its corresponding internal phy node. Another -phandle points to the external PHY node. - -Required properties: - -MAC node: -- compatible : Should be "qcom,fsm9900-emac". -- reg : Offset and length of the register regions for the device -- interrupts : Interrupt number used by this controller -- mac-address : The 6-byte MAC address. If present, it is the default - MAC address. -- internal-phy : phandle to the internal PHY node -- phy-handle : phandle to the external PHY node - -Internal PHY node: -- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii". -- reg : Offset and length of the register region(s) for the device -- interrupts : Interrupt number used by this controller - -The external phy child node: -- reg : The phy address - -Example: - -FSM9900: - -soc { - #address-cells = <1>; - #size-cells = <1>; - - emac0: ethernet@feb20000 { - compatible = "qcom,fsm9900-emac"; - reg = <0xfeb20000 0x10000>, - <0xfeb36000 0x1000>; - interrupts = <76>; - - clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, - <&gcc 6>, <&gcc 7>; - clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", - "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; - - internal-phy = <&emac_sgmii>; - - phy-handle = <&phy0>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins_a>; - }; - - emac_sgmii: ethernet@feb38000 { - compatible = "qcom,fsm9900-emac-sgmii"; - reg = <0xfeb38000 0x1000>; - interrupts = <80>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,fsm9900-pinctrl"; - - mdio_pins_a: mdio { - state { - pins = "gpio123", "gpio124"; - function = "mdio"; - }; - }; - }; - - -QDF2432: - -soc { - #address-cells = <2>; - #size-cells = <2>; - - emac0: ethernet@38800000 { - compatible = "qcom,fsm9900-emac"; - reg = <0x0 0x38800000 0x0 0x10000>, - <0x0 0x38816000 0x0 0x1000>; - interrupts = <0 256 4>; - - clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, - <&gcc 6>, <&gcc 7>; - clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", - "mdio_clk", "tx_clk", "rx_clk", "sys_clk"; - - internal-phy = <&emac_sgmii>; - - phy-handle = <&phy0>; - - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@4 { - reg = <4>; - }; - }; - - emac_sgmii: ethernet@410400 { - compatible = "qcom,qdf2432-emac-sgmii"; - reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */ - <0x0 0x00410000 0x0 0x400>; /* Per-lane digital */ - interrupts = <0 254 1>; - }; -- 2.45.2
