From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Add the DT node for the VBATTB IP along with DT bindings for the clock
it provides.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
Changes in v2:
- update compatibles
- updated clocks and clock-names for clock-controller node
- removed the power domain from the clock-controller as this is
controlled by parent node in v2
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 0d5c47a65e46..78b4e088a3a5 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -72,6 +72,30 @@ scif0: serial@1004b800 {
status = "disabled";
};
+ vbattb: vbattb@1005c000 {
+ compatible = "renesas,r9a08g045-vbattb";
+ reg = <0 0x1005c000 0 0x1000>;
+ ranges = <0 0 0 0x1005c000 0 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tampdi";
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
+ clock-names = "bclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_VBAT_BRESETN>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ vbattclk: clock-controller@1c {
+ compatible = "renesas,r9a08g045-vbattb-clk";
+ reg = <0 0x1c 0 0x10>;
+ clocks = <&vbattb_xtal>;
+ clock-names = "xin";
+ #clock-cells = <0>;
+ status = "disabled";
+ };
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a08g045-cpg";
reg = <0 0x11010000 0 0x10000>;
@@ -299,4 +323,11 @@ timer {
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
+
+ vbattb_xtal: vbattb-xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
};
--
2.39.2
