Add definitions for ADC5 GEN3 virtual channels(combination of ADC channel number and PMIC SID number) used by PM8775. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx> --- .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h new file mode 100644 index 000000000000..84ab07ed73cc --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H + +#include <dt-bindings/iio/adc/qcom,spmi-vadc.h> + +/* ADC channels for PM8775_ADC for PMIC5 Gen3 */ +#define PM8775_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8775_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8775_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8775_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8775_ADC5_GEN3_AMUX1_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8775_ADC5_GEN3_AMUX2_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8775_ADC5_GEN3_AMUX3_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8775_ADC5_GEN3_AMUX4_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8775_ADC5_GEN3_AMUX5_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8775_ADC5_GEN3_AMUX6_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8775_ADC5_GEN3_AMUX1_GPIO9(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8775_ADC5_GEN3_AMUX2_GPIO10(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8775_ADC5_GEN3_AMUX3_GPIO11(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8775_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO) + +/* 100k pull-up2 */ +#define PM8775_ADC5_GEN3_AMUX1_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX2_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX3_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX4_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX5_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX6_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX1_GPIO9_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX2_GPIO10_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX3_GPIO11_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +#define PM8775_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */ -- 2.25.1
