Hi Prabhakar,
On Thu, Jun 27, 2024 at 6:14 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add RZ/V2H(P) CPG driver.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v2->v3
> - Added CLK_PLLDTY
> - Added core clocks sys_0_pclk and iotop_0_shclk
> - Dropped r9a09g057_crit_mod_clks
Thanks for the update!
> --- /dev/null
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> +static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
> + /* External Clock Inputs */
> + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
> + DEF_INPUT("rtxin", CLK_RTXIN),
> + DEF_INPUT("qextal", CLK_QEXTAL),
> +
> + /* PLL Clocks */
> + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
> + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
> + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
> +
> + /* Internal Core Clocks */
> + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
> +
Missing comment "/* Core Clocks */"?
> + DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
> + DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
> +};
> +
> +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = {
__initconst
> + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
> +};
> +
> +static const struct rzv2h_reset r9a09g057_resets[] = {
> + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
> +};
>
> +const struct rzv2h_cpg_info r9a09g057_cpg_info = {
With my suggested changes to [2/3], these two can be __initconst, too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
