Am 11.07.24 um 13:38 schrieb Chen-Yu Tsai:
On Thu, Jul 11, 2024 at 7:13 PM Alex Bee <knaerzche@xxxxxxxxx> wrote:
Am 11.07.24 um 11:17 schrieb Chen-Yu Tsai:
On Thu, Jul 11, 2024 at 4:44 PM Jonas Karlman <jonas@xxxxxxxxx> wrote:
Hi Anand,
On 2024-07-11 08:09, Anand Moon wrote:
Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
signals.Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices.
Used by root complex to endpoint depending on the power state.
PERST is referred to as a fundamental reset. PERST should be held low
until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the
beginning of link initialization.
WAKE signal is an active-low signal that is used to return the PCIe
interface to an active state when in a low-power state.
CLKREQ signal is also an active-low signal and is used to request the
reference clock.
Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
---
V2: Update the commit messge to describe the changs.
use pinctl group as its pre define in pinctl dtsi
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 2e7512676b7e..ab3a20986c6a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -301,7 +301,7 @@ &pcie30phy {
&pcie3x4 {
pinctrl-names = "default";
- pinctrl-0 = <&pcie3_rst>;
+ pinctrl-0 = <&pcie30x4m1_pins>;
Use of the existing pcie30x4m1_pins group may not be fully accurate for
the PERST pin. The use of reset-gpios indicate that the PERST pin is
used with GPIO function and the driver will implicitly change the
function from perstn_m1 to GPIO. So this may not be best representation
of the hw, hence my initial suggestion, something like:
pcie30x4_pins: pcie30x4-pins {
rockchip,pins =
<4 RK_PB4 4 &pcfg_pull_none>,
<4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>,
<4 RK_PB5 4 &pcfg_pull_none>;
};
Similar change should probably also be done for pcie2x1l0 and pcie2x1l2,
not just pcie3x4.
Can we consider implementing strict mode in the pinctrl driver so we don't
have to keep doing this GPIO + pinmux dance?
This is not about drivers, this is DT which is independent from drivers.
Jonas and I had discussion recently on u-boot mailing list with somebody
using Open/FreeBSD about exact that topic. Pinctrl mux settings should be
very explicit, even if it is not required by the linux-driver.
The hardware also prevents you from using GPIOs with any other mux setting.
That is already implied by the compatible string and doesn't need to be
spelled out. The strict driver mode merely enforces this hardware limitation
without the very explicit setting. One could also say that the driver is
wrong to support conflicting settings.
ChenYu
"The" driver is in fact not correct here, since it's two actually two
drivers: pinctrl and gpio, two subsystems and separate HW blocks (not very
clear, but it's at least configured in different mmio regions). So with
what you are suggesting you want one driver to implicitly configure the
other and expect every OS to have such methods? Broad ...
Alex
Alex
ChenYu
Regards,
Jonas
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
@@ -341,10 +341,6 @@ pcie2_2_rst: pcie2-2-rst {
};
pcie3 {
- pcie3_rst: pcie3-rst {
- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
pcie3_vcc3v3_en: pcie3-vcc3v3-en {
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
base-commit: 34afb82a3c67f869267a26f593b6f8fc6bf35905
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