On Thu, Jul 11, 2024 at 11:54:15AM +0200, Konrad Dybcio wrote: > On 11.07.2024 11:02 AM, Johan Hovold wrote: > > The DWC PCIe controller can be used with its internal MSI controller or > > with an external one such as the GICv3 Interrupt Translation Service > > (ITS). > > > > Add the msi-map properties needed to use the GIC ITS. This will also > > make Linux switch to the ITS implementation, which allows for assigning > > affinity to individual MSIs. > > > > Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx> > > --- > > X1E CRD throws tons of correctable errors with this on PCIe6a: > > [ 9.358915] pcieport 0007:00:00.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Receiver ID) > [ 9.358916] pcieport 0007:00:00.0: device [17cb:0111] error status/mask=00000001/0000e000 > [ 9.358917] pcieport 0007:00:00.0: [ 0] RxErr > [ 9.358921] pcieport 0007:00:00.0: AER: Multiple Correctable error message received from 0007:00:00.0 > [ 9.358952] pcieport 0007:00:00.0: AER: found no error details for 0007:00:00.0 > [ 9.358953] pcieport 0007:00:00.0: AER: Multiple Correctable error message received from 0007:00:00.0 > [ 9.359003] pcieport 0007:00:00.0: AER: found no error details for 0007:00:00.0 > [ 9.359004] pcieport 0007:00:00.0: AER: Multiple Correctable error message received from 0007:01:00.0 > [ 9.359008] pcieport 0007:00:00.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Transmitter ID) > [ 9.359009] pcieport 0007:00:00.0: device [17cb:0111] error status/mask=00001001/0000e000 > [ 9.359010] pcieport 0007:00:00.0: [ 0] RxErr > [ 9.359011] pcieport 0007:00:00.0: [12] Timeout What branch are you using? Abel reported seeing this with his branch which has a few work-in-progress patches that try to enable 4-lane PCIe. There are no errors with my wip branch based on rc7, and I have the same drive as Abel. Also note that the errors happen also without this patch applied, they are just being reported now. Johan
