Am Mittwoch, 10. Juli 2024, 22:08:33 CEST schrieb Shenwei Wang:
> For the i.MX93 SoC, the clock rate for the IP of STMMAC EQOS is 315 MHz.
Are you talking about enet_qos (IMX93_CLK_ENET_QOS_GATE)?
Downstream 6.1 kernel shows:
sys_pll_pfd2 1 1 0 625000000 0 0 50000 Y
wakeup_axi_root 4 4 0 312500000 0 0 50000 Y
enet_qos 5 5 0 312500000 0 0 50000 Y
Also RM gives a maximum of 312.5 MHz.
> According to the following mapping table from the i.MX93 reference manual,
> this clock rate corresponds to a CSR value of 6.
>
> 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102
> 0101: CSR clock = 250-300 MHz; MDC clock = CSR clock/124
> 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204
> 0111: CSR clock = 500-800 MHz; MDC clock = CSR clock/324
As the old value is 0 you should at least add that entry as well.
But AFAICS enet_qos is passed as clock 'mem' to this device.
So instead of hard-coding this into DT, this divider should be calculated from actual
enet_qos clock.
Best regards,
Alexander
> Signed-off-by: Shenwei Wang <shenwei.wang@xxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx93.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
> index 4a3f42355cb8..a0993022c102 100644
> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
> @@ -1105,7 +1105,7 @@ eqos: ethernet@428a0000 {
> <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> assigned-clock-rates = <100000000>, <250000000>;
> intf_mode = <&wakeupmix_gpr 0x28>;
> - snps,clk-csr = <0>;
> + snps,clk-csr = <6>;
> nvmem-cells = <ð_mac2>;
> nvmem-cell-names = "mac-address";
> status = "disabled";
>
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