This patch series aims to add support for RZ/G2UL DU.
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
The output of LCDC is connected display parallel interface (DPI) and
supports a maximum resolution of WXGA along with 2 RPFs to support the
blending of two picture layers and raster operations (ROPs)
It is similar to LCDC IP on RZ/G2L SoCs, but does not have DSI interface.
v1->v2:
* Updated cover letter header "DU IP->Display Unit".
* Updated commit description related to non ABI breakage for patch#3.
* Added Ack from Conor for binding patches.
Biju Das (9):
media: dt-bindings: media: renesas,vsp1: Document RZ/G2UL VSPD
bindings
media: dt-bindings: media: renesas,fcp: Document RZ/G2UL FCPVD
bindings
dt-bindings: display: renesas,rzg2l-du: Document RZ/G2UL DU bindings
clk: renesas: r9a07g043: Add LCDC clock and reset entries
drm: renesas: rz-du: Add RZ/G2UL DU Support
arm64: dts: renesas: r9a07g043u: Add vspd node
arm64: dts: renesas: r9a07g043u: Add fcpvd node
arm64: dts: renesas: r9a07g043u: Add DU node
arm64: dts: renesas: r9a07g043u11-smarc: Enable DU
.../bindings/display/renesas,rzg2l-du.yaml | 32 ++++-
.../bindings/media/renesas,fcp.yaml | 2 +
.../bindings/media/renesas,vsp1.yaml | 1 +
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 49 ++++++++
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 111 ++++++++++++++++++
drivers/clk/renesas/r9a07g043-cpg.c | 12 ++
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 9 +-
drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 11 ++
8 files changed, 223 insertions(+), 4 deletions(-)
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2.43.0
