From: Richard Zhu <hongxing.zhu@xxxxxxx> Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. clock-names align dwc common naming convension. Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx> Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx> Signed-off-by: Frank Li <Frank.Li@xxxxxxx> --- .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 8b8d77b1154b5..1e05c560d7975 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -30,6 +30,7 @@ properties: - fsl,imx8mm-pcie - fsl,imx8mp-pcie - fsl,imx95-pcie + - fsl,imx8q-pcie clocks: minItems: 3 @@ -184,6 +185,21 @@ allOf: - const: pcie_bus - const: pcie_aux + - if: + properties: + compatible: + enum: + - fsl,imx8q-pcie + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + unevaluatedProperties: false examples: -- 2.34.1