CV1800/SG200x SoCs integrate a USB 2.0 phy and a USB controller based
on dwc2 IP. Add device tree nodes for these peripherals.
Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
---
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..06461f1f1986 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -61,6 +61,18 @@ clk: clock-controller@3002000 {
#clock-cells = <1>;
};
+ usb_phy: usb-phy@3006000 {
+ compatible = "sophgo,cv1800-usb-phy";
+ reg = <0x3006000 0x60>, <0x3000048 0x4>;
+ reg-names = "phy", "pin";
+ clocks = <&clk CLK_APB_USB>,
+ <&clk CLK_USB_125M>,
+ <&clk CLK_USB_33K>,
+ <&clk CLK_USB_12M>;
+ clock-names = "apb", "125m", "33k", "12m";
+ #phy-cells = <0>;
+ };
+
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
@@ -297,6 +309,17 @@ sdhci0: mmc@4310000 {
status = "disabled";
};
+ usb_otg: usb@4340000 {
+ compatible = "sophgo,cv1800-usb";
+ reg = <0x4340000 0x10000>;
+ clocks = <&clk CLK_AXI4_USB>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb_phy>;
+ phy-names = "usb2-phy";
+ };
+
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
--
2.45.2
