On Mon, 10 Jun 2024 04:09:12 PDT (-0700), Conor Dooley wrote:
Hey all,
Here's some patches that add an Erratum to enable non-coherent DMA
support for PolarFire SoC. By nature of being an FPGA, and due to the
PCIe root ports being only 32-bit capable, many bitstreams configure the
FPGA fabric such that peripherals in the fabric become non-coherent. The
PCIe root ports on PolarFire SoC are connected to the core-complex via
the fabric, and therefore can be (and regularly are) made DMA
non-coherent. The Icicle Kit Reference Design has been configuring the
PCIe root port in this manner since late 2022 and in a way unsupported
by mainline since earlier that year. Adding this non-coherent DMA
support makes PCIe functional on those FPGA designs. Daire did almost all
the work to figure out how to support these kinds of designs, and this
series depends on his patches to introduce the required dma-ranges
handling for the root port driver:
https://lore.kernel.org/linux-pci/20240531085333.2501399-1-daire.mcnamara@xxxxxxxxxxxxx/
The final patch depends on:
https://lore.kernel.org/linux-pci/20240527-slather-backfire-db4605ae7cd7@wendy/
I'm not sure if an Erratum is really the right way to go about doing
this, but I didn't want to make ARCH_MICROCHIP depend on NONPORTABLE.
An alternative would be to add a menu under drivers/soc like Renesas
does and allow it to be toggled as an option there instead.
Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
if you want to take this via some other tree.
I don't see any issue calling it an erratum, if it lets us keep building
generic kernels for these systems that seems like a good enough agrument
to me.
Thanks,
Conor.
CC: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
CC: Palmer Dabbelt <palmer@xxxxxxxxxxx>
CC: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
CC: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
CC: Rob Herring <robh@xxxxxxxxxx>
CC: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
CC: Samuel Holland <samuel.holland@xxxxxxxxxx>
CC: linux-riscv@xxxxxxxxxxxxxxxxxxx
CC: devicetree@xxxxxxxxxxxxxxx
Conor Dooley (5):
cache: ccache: allow building for PolarFire
cache: ccache: add mpfs to nonstandard cache ops list
RISC-V: Add an MPFS erratum for PCIe
riscv: dts: microchip: modify memory map & add dma-ranges for pcie on
icicle
riscv: dts: microchip: update pcie reg properties
arch/riscv/Kconfig.errata | 19 +++++
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 77 ++++++++++++-------
.../boot/dts/microchip/mpfs-icicle-kit.dts | 44 +++++++++--
.../dts/microchip/mpfs-m100pfs-fabric.dtsi | 6 +-
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 6 +-
drivers/cache/Kconfig | 2 +-
drivers/cache/sifive_ccache.c | 2 +
7 files changed, 116 insertions(+), 40 deletions(-)
