On Thu, Jun 27, 2024 at 08:10:48PM +0300, Serge Semin wrote: > On Thu, Jun 27, 2024 at 04:51:22PM +0100, Conor Dooley wrote: > > On Thu, Jun 27, 2024 at 03:41:26AM +0300, Serge Semin wrote: > > > + clocks: > > > + description: > > > + Both MCI and APB3 interfaces are supposed to be equipped with a clock > > > + source connected via the clk_csr_i line. > > > + > > > + PCS/PMA layer can be clocked by an internal reference clock source > > > + (phyN_core_refclk) or by an externally connected (phyN_pad_refclk) clock > > > + generator. Both clocks can be supplied at a time. > > > + minItems: 1 > > > + maxItems: 3 > > > + > > > + clock-names: > > > + oneOf: > > > + - minItems: 1 > > > + items: > > > + - enum: [core, pad] > > > + - const: pad > > > + - minItems: 1 > > > + items: > > > + - const: pclk > > > + - enum: [core, pad] > > > + - const: pad > > > > > While reading this, I'm kinda struggling to map "clk_csr_i" to a clock > > name. Is that pclk? And why pclk if it is connected to "clk_csr_i"? > > Right. It's "pclk". The reason of using the "pclk" name is that it has > turned to be a de-facto standard name in the DT-bindings for the > peripheral bus clock sources utilized for the CSR-space IO buses. > Moreover the STMMAC driver responsible for the parental DW *MAC > devices handling also has the "pclk" name utilized for the clk_csr_i > signal. So using the "pclk" name in the tightly coupled devices (MAC > and PCS) for the same signal seemed a good idea. It is? That's really just the name of the bus clock for APB (Arm Peripheral Bus). If there's a name that matches the docs, use that. Though I'd drop 'clk_' part. Rob
