Hi Claudiu,
On Tue, Jun 25, 2024 at 2:14 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Fast mode plus is available on most of the IP variants that RIIC driver
> is working with. The exception is (according to HW manuals of the SoCs
> where this IP is available) the Renesas RZ/A1H. For this, patch
> introduces the struct riic_of_data::fast_mode_plus.
>
> Fast mode plus was tested on RZ/G3S, RZ/G2{L,UL,LC}, RZ/Five by
> instantiating the RIIC frequency to 1MHz and issuing i2c reads on the
> fast mode plus capable devices (and the i2c clock frequency was checked on
> RZ/G3S).
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/i2c/busses/i2c-riic.c
> +++ b/drivers/i2c/busses/i2c-riic.c
> @@ -407,6 +413,9 @@ static int riic_init_hw(struct riic_dev *riic)
> riic_writeb(riic, 0, RIIC_ICSER);
> riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3);
>
> + if (info->fast_mode_plus && t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ)
> + riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER);
Unless FM+ is specified, RIIC_ICFER is never written to.
Probably the register should always be initialized, also to make sure
the FMPE bit is cleared when it was set by the boot loader, but FM+
is not to be used.
> +
> riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
>
> pm_runtime_mark_last_busy(dev);
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
