On Thu, Jun 27, 2024 at 9:23 AM Pafford, Robert J. <pafford.9@xxxxxxxxxxxxxxxxxxx> wrote: > > Frank Oltmanns <frank@xxxxxxxxxxxx> writes: > > > Hi Robert, > > > > 26.06.2024 18:03:24 Pafford, Robert J. <pafford.9@xxxxxxxxxxxxxxxxxxx>: > > > >> Hi Frank, > >> > >> Moving to a new for loop makes sense. Let me know when you have a patch > > > > The patch is here, strange you didn't receive it: > > https://lore.kernel.org/all/20240623-sunxi-ng_fix_common_probe-v1-1-7c97e32824a1@xxxxxxxxxxxx/ > > Ah, this must have slipped through my inbox. I just applied it on my board and it is > now cooperating with the min/max clock rates! Please reply to the thread and give a Tested-by. ChenYu > > > >> and I'll be glad to test it on my board. I do also wonder if this may > >> have contributed to some of the HDMI issues seen in the other thread. > > > > My thought's exactly! > > > > Best regards, > > Frank > > > >> > >> Best, > >> Robert > >> > >>> Hi Robert, > >>> > >>> I'm truly sorry for the trouble the patch has caused you and for my late > >>> reply! > >>> > >>> On 2024-06-14 at 23:52:08 +0000, "Pafford, Robert J." <pafford.9@xxxxxxxxxxxxxxxxxxx> wrote: > >>>>> The Allwinner SoC's typically have an upper and lower limit for their > >>>>> clocks' rates. Up until now, support for that has been implemented > >>>>> separately for each clock type. > >>>>> > >>>>> Implement that functionality in the sunxi-ng's common part making use of > >>>>> the CCF rate liming capabilities, so that it is available for all clock > >>>>> types. > >>>>> > >>>>> Suggested-by: Maxime Ripard <mripard@xxxxxxxxxx> > >>>>> Signed-off-by: Frank Oltmanns <frank@xxxxxxxxxxxx> > >>>>> Cc: stable@xxxxxxxxxxxxxxx > >>>>> --- > >>>>> drivers/clk/sunxi-ng/ccu_common.c | 19 +++++++++++++++++++ > >>>>> drivers/clk/sunxi-ng/ccu_common.h | 3 +++ > >>>>> 2 files changed, 22 insertions(+) > >>>> > >>>> This patch appears to cause a buffer under-read bug due to the call to 'hw_to_ccu_common', which assumes all entries > >>>> in the desc->hw_clocks->hws array are contained in ccu_common structs. > >>>> > >>>> However, not all clocks in the array are contained in ccu_common structs. For example, as part > >>>> of the "sun20i-d1-ccu" driver, the "pll-video0" clock holds the 'clk_hw' struct inside of a 'clk_fixed_factor' struct, > >>>> as it is a fixed factor clock based on the "pll-video0-4x" clock, created with the CLK_FIXED_FACTOR_HWS macro. > >>>> This results in undefined behavior as the hw_to_ccu_common returns an invalid pointer referencing memory before the > >>>> 'clk_fixed_factor' struct. > >>>> > >>> > >>> Great catch! At first glance, it seems to me that calling > >>> clk_hw_set_rate_range() in sunxi_ccu_probe() should not have happenend > >>> in the loop that iterates over the hw_clks. > >>> > >>> Instead we should add one more loop that iterates over the ccu_clks. > >>> Note, that there is already one such loop but, unfortunately, we can't > >>> use that as it happens before the hw_clks loop and we can only call > >>> clk_hw_set_rate_range() after the hw_clk has been registered. > >>> > >>> Hence, I propose to move the offending code to a new loop: > >>> for (i = 0; i < desc->num_ccu_clks; i++) { > >>> struct ccu_common *cclk = desc->ccu_clks[i]; > >>> > >>> if (!cclk) > >>> continue; > >>> > >>> if (cclk->max_rate) > >>> clk_hw_set_rate_range(&cclk->hw, common->min_rate, > >>> common->max_rate); > >>> else > >>> WARN(cclk->min_rate, > >>> "No max_rate, ignoring min_rate of clock %d - %s\n", > >>> i, cclk->hw.init->name); > >>> } > >>> > >>> I haven't tested (or even compiled) the above, but I'll test and send a > >>> patch within the next few days for you to test. > >>> > >>> Thanks again, > >>> Frank > >>> > >>>> > >>>> I have attached kernel warnings from a system based on the "sun8i-t113s.dtsi" device tree, where the memory contains > >>>> a non-zero value for the min-rate but a zero value for the max-rate, triggering the "No max_rate, ignoring min_rate" > >>>> warning in the 'sunxi_ccu_probe' function. > >>>> > >>>> [...] > > Thanks, > Robert
