Match the capitalization of the subject line, s/add/Add/ as in
previous patch.
On Wed, Jun 26, 2024 at 01:45:42PM +0300, Stanimir Varbanov wrote:
> Not all PCIe can control the phy block, add a flag
> in config structure to take that fact into account.
>
> Signed-off-by: Stanimir Varbanov <svarbanov@xxxxxxx>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 4ca509502336..ff8e5e672ff0 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -224,6 +224,7 @@ enum pcie_type {
> struct pcie_cfg_data {
> const int *offsets;
> const enum pcie_type type;
> + bool phy_controllable;
> void (*perst_set)(struct brcm_pcie *pcie, u32 val);
> void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
> };
> @@ -1301,11 +1302,17 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
>
> static inline int brcm_phy_start(struct brcm_pcie *pcie)
> {
> + if (!pcie->cfg->phy_controllable)
> + return 0;
> +
> return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
> }
>
> static inline int brcm_phy_stop(struct brcm_pcie *pcie)
> {
> + if (!pcie->cfg->phy_controllable)
> + return 0;
> +
> return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
> }
>
> @@ -1498,6 +1505,7 @@ static const int pcie_offsets_bmips_7425[] = {
> static const struct pcie_cfg_data generic_cfg = {
> .offsets = pcie_offsets,
> .type = GENERIC,
> + .phy_controllable = true,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> };
> @@ -1505,6 +1513,7 @@ static const struct pcie_cfg_data generic_cfg = {
> static const struct pcie_cfg_data bcm7425_cfg = {
> .offsets = pcie_offsets_bmips_7425,
> .type = BCM7425,
> + .phy_controllable = true,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> };
> @@ -1512,6 +1521,7 @@ static const struct pcie_cfg_data bcm7425_cfg = {
> static const struct pcie_cfg_data bcm7435_cfg = {
> .offsets = pcie_offsets,
> .type = BCM7435,
> + .phy_controllable = true,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> };
> @@ -1519,6 +1529,7 @@ static const struct pcie_cfg_data bcm7435_cfg = {
> static const struct pcie_cfg_data bcm4908_cfg = {
> .offsets = pcie_offsets,
> .type = BCM4908,
> + .phy_controllable = true,
> .perst_set = brcm_pcie_perst_set_4908,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> };
> @@ -1532,6 +1543,7 @@ static const int pcie_offset_bcm7278[] = {
> static const struct pcie_cfg_data bcm7278_cfg = {
> .offsets = pcie_offset_bcm7278,
> .type = BCM7278,
> + .phy_controllable = true,
> .perst_set = brcm_pcie_perst_set_7278,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
> };
> @@ -1539,6 +1551,7 @@ static const struct pcie_cfg_data bcm7278_cfg = {
> static const struct pcie_cfg_data bcm2711_cfg = {
> .offsets = pcie_offsets,
> .type = BCM2711,
> + .phy_controllable = true,
> .perst_set = brcm_pcie_perst_set_generic,
> .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> };
> --
> 2.43.0
>
