On Mon, Jun 24, 2024 at 08:49:54PM -0400, Jesse Taube wrote: > > Zicclsm Misaligned loads and stores to main memory regions with both > > the cacheability and coherence PMAs must be supported. > > Note: > > This introduces a new extension name for this feature. > > This requires misaligned support for all regular load and store > > instructions (including scalar and vector) but not AMOs or other > > specialized forms of memory access. Even though mandated, misaligned > > loads and stores might execute extremely slowly. Standard software > > distributions should assume their existence only for correctness, > > not for performance. > > Detecing zicclsm allows the kernel to report if the > hardware supports misaligned accesses even if support wasn't probed. > > This is useful for usermode to know if vector misaligned accesses are > supported. > > Signed-off-by: Jesse Taube <jesse@xxxxxxxxxxxx> > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Reviewed-by: Andy Chiu <andy.chiu@xxxxxxxxxx> > --- > V1 -> V2: > - Add documentation for Zicclsm > - Move Zicclsm to correct location > V2 -> V3: > - No changes > --- > Documentation/arch/riscv/hwprobe.rst | 3 +++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > arch/riscv/kernel/sys_hwprobe.c | 1 + > 5 files changed, 7 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index df5045103e73..7085a694b801 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -207,6 +207,9 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is > supported, as defined by version 1.0 of the RISC-V Vector extension manual. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported as > + defined in the RISC-V RVA Profiles Specification. I'd rather that you regurgitated the definition here, these keys/values cannot change their meaning, but RISC-V specs are not stable. Cheers, Conor.
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