On Wed, 2015-03-04 at 14:31 -0600, tthayer@xxxxxxxxxxxxxxxxxxxxx wrote: > From: Thor Thayer <tthayer@xxxxxxxxxxxxxxxxxxxxx> > > The Altera Arria10 SoC requires 32 bit accesses to peripherals. The > DesignWare SPI peripheral registers are on 32bit boundaries so this > patch is minimal. Function pointers are used to select 32bit access > or 16bit accesses. So, what is exactly the issue when we read only half of the register? Bus lock, or what? > > Thor Thayer (2): > dt-binding: spi: spi-dw: Select 16b or 32b access for Designware SPI > spi: dw-spi: Pointers select 16b vs. 32b DesignWare access > > Documentation/devicetree/bindings/spi/spi-dw.txt | 1 + > drivers/spi/spi-dw-mmio.c | 7 +++- > drivers/spi/spi-dw.c | 38 +++++++++++++--------- > drivers/spi/spi-dw.h | 10 +++--- > 4 files changed, 35 insertions(+), 21 deletions(-) > -- Andy Shevchenko <andriy.shevchenko@xxxxxxxxx> Intel Finland Oy -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
